The present invention relates to a semiconductor device and a method of forming the same, and more particularly to a ball grid array semiconductor package.
FIG. 1 is a fragmentary cross sectional elevation view illustrative of a first conventional ball grid array semiconductor package having a single wiring layer which has high electrical performance. This first conventional ball grid array semiconductor package is disclosed in IEEE, 1996, Electronic Components and Technology Conference "TBGA Bond Process For Ground And Power Planes Connections."
The first conventional ball grid array semiconductor package has a metal heat spreader 33. The metal heat spreader 33 has a flat upper surface and a depressed portion. A mounting member 32 is provided on the depressed portion so that a semiconductor chip 31 is mounted on the mounting member 32 on the depressed portion. A power plane 34 is provided via an adhesive 37 on the flat upper surface of the metal heat spreader 33. A polyimide pattern 36 as an organic insulator is lamninated via the adhesive 37 on the power plane 34. A copper foil wiring pattern 35 is provided by a tape automated bonding to electrically connect electrodes of the semiconductor chip 3 into the metal heat spreader 33 and the power plane 34.
The above first conventional ball grid array semiconductor package utilizing the tape automated bonding technique has the following disadvantages. It is required to form tape automated bonding tapes for every product types of the ball grid array semiconductor packages separately. Further, it is required to carrying out an additional process for adhering the tape automated bonding tape onto the metal plate or adhering a metal plate onto the tape automated bonding semiconductor chip. Those requirements result in an increase in manufacturing costs.
FIG. 2 is a fragmentary cross sectional elevation view illustrative of a second conventional semiconductor package. This second conventional semiconductor package is disclosed in U.S. Pat. No. 5,153,385. The second conventional semiconductor package has a metal heat spreader 38 having a single flat upper surface. A first organic substrate 39 entirely coated with a ground potential plane 40 is adhered on the single flat upper surface of the metal heat spreader 38 except for a predetermined chip area on which a semiconductor chip 42 is provided. A second organic substrate 43 having signal wiring patterns 41 is also adhered on an upper surface of the ground potential plane 40 coating the first organic substrate 39. Ground electrodes of the semiconductor chip 42 are wire-bonded to the ground potential plane 40. Signal electrodes 45 of the semiconductor chip 42 are wire-bonded to the signal wiring patterns 41 on the second organic substrate 43. The signal wiring patterns 41 is electrically isolated by the second organic substrate 43 from the ground potential plane 40, so that the signal wiring patterns 41 have a predetermined impedance.
The above second conventional semiconductor package has the following disadvantages. Two organic substrates 39 and 43 are laminated over the metal heat spreader 38. This makes the semiconductor package expensive. Since the heat spreader 38 is connected through the ground potential plane 40 to the ground electrodes 44 of the semiconductor chip 42, thus it is difficult that the potential of the heat spreader 38 is grounded and also the potential of the semiconductor chip 42 is grounded. Since further the above second conventional semiconductor package has been formed by bombing the substrates, thus this structure may permit entry of moisture into the bonding surface between the substrates, whereby a reliability of the semiconductor memory device is deteriorated.
In the above circumstances, it had been required to develop a novel semiconductor package free from the above disadvantages.